Electrical writable and erasable non-volatile memory cells, which can especially be used in a virtual ground NOR architecture, also include so-called charge trapping memory cells, in which, between the channel region and/or the source/drain region and the gate electrode, there is a part of the gate dielectric having a non-conducting memory layer between boundary layers for the trapping of charge carriers and thus for changing the programming state of the memory cell. Such memory cells are described for example in U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725 and PCT Patent Publication WO 99/60631. In these memory cells each boundary layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon.
Charge-trapping memory cells are preferably programmed by channel hot electrons (CHE) and can be erased with hot holes from the channel region or by Fowler-Nordheim tunnels. A SONOS memory cell provided for a special operating mode with a read voltage (reverse-read) applied in the opposite direction to the programming process, having a thickness of the boundary layers matched to this operating mode, is usually designated as an NROM memory cell. Further details on this can be found in Boaz Eitan et al.: “NROM: A Novel Localized Trapping, 2-Bit Non-Volatile Memory Cell” in IEEE Electron Device Letters 21, 543–545 (2000).
The memory layer of a charge-trapping memory cell is located between a boundary layer comprising a material having a higher band gap than the band gap of the memory layer so that the charge carriers captured in the memory layer remain localized there. A nitride is preferably considered as material for the memory layer. An oxide is primarily suitable as surrounding material. As an example of such an oxide-nitride-oxide (ONO) memory layer sequence in the material system of silicon, the silicon nitride memory layer is provided with a band gap of about 5 eV. The surrounding boundary layers are silicon oxide having a band gap of about 9 eV.
The memory layer can be a different material whose band gap is smaller than the band gap of the boundary layers wherein the difference of the band gaps should be as large as possible for good electrical confinement of the charge carriers. In conjunction with silicon oxide as the boundary layer, for example, tantalum oxide, hafnium silicate, titanium oxide (in the case of a stoichiometric composition TiO2), zirconium oxide (in the case of a stoichiometric composition ZrO2), aluminum oxide (in the case of a stoichiometric composition Al2O3), or intrinsically conducting (undoped) silicon can be used as the material of the memory layer.
Such a 2-bit NROM memory cell is programmed, as described for example in PCT Patent Publication WO 98/03977, such that by means of a gate voltage and a drain source voltage in the channel region of the memory cell, a vertical and a lateral electric field is produced which accelerates the electrons along the channel length. Some electrons are accelerated such that in the vicinity of the drain region where the electric field is strongest, they jump over the potential barrier and reach the nitride layer. In this way, the threshold voltage of the channel region changes, which can be detected by applying a read voltage in the reverse direction. The second bit in this memory cell is programmed by exchanging drain and source compared with the previous described programming process for writing the memory cell and thus the significant adjustment of charges into the charge-trapping layer. In this way, 2-bit information can be stored in a non-volatile memory cell, such as an NROM cell for example.
A disadvantage of this known procedure is that during incorporation of charges into the charge trapping layer on one side of such a cell, reactions are observed on the threshold voltage of the respectively other side of the memory cell. So-called crosstalk thus results. The crosstalk increases with increasing difference between the threshold voltages of the two sides of a cell.
That crosstalk may have the following influences. For reading a NROM memory cell a particular gate voltage and particular drain/source voltage is supplied to the cell. Drain and source are defined so that the desired part of the cell will be read. If no charge is stored in the charge-trapping layer a significant drain current will flow if a specific gate voltage is supplied. When a particular charge is stored in the charge-trapping layer (the nitride layer), this charge will hinder the development of a channel between source and drain and no drain current will flow at the same gate voltage or the drain current will be at least significantly lower. This behavior is viewable in a usual transfer characteristic. Programming of one side of the NROM cell can result in a modification of the transfer characteristic of the other side so that, for an example, a drain current will flow even when no charge was stored within the charge trapping layer.
As the technology is further developed, the effective channel length and thus the physical distance between the charges of both sides of a cell decreases. This results in stronger crosstalk. It can thus be reckoned that in the future there will be an increased number of errors that come about as a result of crosstalk.